Research Overview  

Multivariate Statistical Analysis of Large Scale Data: The goal is to provide tools that will make it possible to analyze the massive amounts of data produced by hardware performance counters in large-scale parallel applications. Several statistical methods will be employed to assemble performance counter data into similar groups that can more easily interpreted giving important information about the performance of the application. Collection and Validation of Application Benchmarking and Performance Data: The aim of this project is to provide DoD application programmers with tools to automate the collection of performance data from applications running on DoD HPC Center platforms and to provide metrics to understand, interpret, and analyze performance counters and communication data. Performance Counter Assessment: Most state-of-the-art microprocessors have on-chip hardware counters, which can be used to monitor performance-related events, such as cache misses.  These event counts can be used to evaluate application performance and identify performance bottlenecks or unexpected program or architecture characteristics. We analyze performance counter data in order to

• understand the data obtained from hardware performance counters,
• determine the reasons why the data may be different from what is expected,
• quantify the overhead associated with the counter interface, 
• derive metrics from the gathered data that characterize the performance of application and facilitate its tuning, and
• work with vendors and/or tool builders to fix errors.

The work, which is being done in collaboration with the University of Tennessee-Knoxville (UTK), supported by the Department of Defense (DoD) PET Program (Programming Environment and Training), will provide DoD application programmers with information that will allow them to effectively use performance data collected via UTK's PAPI (Performance Application Programming Interface).